1. Field of the Invention
The present invention relates to a demodulating circuit for use in a receiving circuit that receives burst signals such as the signals employed in mobile wireless communication systems and fiber-optic communication systems.
2. Description of the Related Art
The burst signals employed in communication systems are coded according to coding systems that allow runs of consecutive high (‘1’) or low (‘0’) bits up to a specified maximum run length. The demodulating circuit in the receiver must be capable of receiving such runs without error.
Some communication systems that employ burst signals employ different time intervals for transmitting and receiving bursts. Some of these communication systems also separate the transmitting and receiving intervals by quiescent states, in which power is supplied but neither transmission nor reception is performed. During a quiescent state, the receiver receives a long run of identical ‘1’ or ‘0’ symbols. The run ends abruptly when a signal burst begins, because the burst includes both ‘1’ and ‘0’ symbols. At the end of the burst, the quiescent state resumes, and another long run of identical ‘1’ or ‘0’ symbols begins. The circuit for demodulating the received signal demodulates both the burst of signal pulses and the long runs of identical ‘1’ or ‘0’ symbols, and supplies a positive-phase or a negative-phase demodulated output signal at prescribed high and low logic levels.
When the amplitude of the received pulses is small, which is the case in an optical receiving circuit, it is necessary to amplify the received signal preparatory to demodulation. If the received pulse signal is amplified by, for example, a capacitively coupled multi-stage amplifier, which is often the case, the peak value of the output signal envelope, or its amplitude, varies depending on three factors listed below. The demodulating circuit must be able to generate logic outputs corresponding to the ‘0’ and ‘1’ values of the original pulse signal even when the amplified pulse signal varies according to these factors, which are:                (1) whether the received pulse signal is amplified in a linear or non-linear (limited) amplification range;        (2) the ratio of 1's to 0's in the received pulse signal; and        (3) the lengths of runs of 1's or 0's in the received pulse signal.        
In an optical receiving circuit disclosed on p. 3 and in FIG. 1 of Japanese Unexamined Patent Application Publication No. 8-84160 (hereinafter, Reference 1), for example, the received optical signal is converted to a current signal by a photodiode, then to a voltage signal by a preamplifier. The preamplified but still weak voltage signal is amplified by a main amplifier that also performs offset compensation, and is then converted to a logic signal by a comparator element. This configuration is known to enable the optical receiving circuit to generate a logic output signal with low duty distortion, even during short bursts.
In another optical receiving circuit, disclosed on pp. 3-4 and in FIG. 1 of Japanese Unexamined Patent Application Publication No. 10-163828 (hereinafter, Reference 2), for example, in addition to the configuration described in Reference 1, a fixed offset voltage source is added to the offset compensator in the final amplifier stage preceding the comparator element. The fixed offset voltage source holds the output of the comparator element at the low logic level during reception of runs of ‘0’ symbols over which the peak hold circuit in the offset compensating main amplifier cannot maintain a constant peak value. In particular, the logic output of the comparator element is held at the low level during quiescent states in which long runs of ‘0’ symbols are received.
In wireless and other communication systems that use frequency-shift keying (FSK), variations in the direct-current (dc) offset of the demodulated or detected signal occur due to the influence of the difference between the frequency of the FSK signal and the predefined carrier frequency. These variations are dealt with in U.S. Pat. No. 6,104,238 (hereinafter, Reference 3) by smoothing the detected signal and varying its center frequency so as to track the dc offset variations.
U.S. Pat. No. 5,412,692 (hereinafter, Reference 4) discloses another method of tracking dc offset variations, namely by detecting the maximum and minimum levels of the detected output signal and using a potential midway between them as a reference potential for the comparator circuit.
In a communication system in which transmission and reception periods alternate, or are separated by quiescent states, when communication switches over to the receiving state, the received signal arrives in a burst that dynamically alters the dc potential of the detected signal. To enable the receiver to adjust to the new dc potential, a preamble pattern is generally added at the beginning of each burst. The preamble pattern differs, however, depending on the communication system employed, and is only four bits long in some systems. To demodulate a received signal with such a short preamble pattern, the receiving circuit needs to be able to track dynamically changing dc potentials rapidly.
In general, however, the ability to track dc potential variations rapidly must be traded off against the ability to receive long runs of identical symbols without error: if the dc potential tracking capability is improved, the run-length tolerance is reduced.
In the circuit configuration disclosed in Reference 1, during a quiescent state in which a long run of ‘0’ symbols is received, the differential input to the comparator element becomes zero due to the offset compensating operation. The capability to track dc potential variations rapidly is thus improved at the cost of having the logic output of the comparator element sometimes become unstable.
The circuit configuration disclosed in Reference 2 improves the capability to receive runs of identical symbols without error, but the effectiveness of the offset compensating operation in maintaining the correct duty cycle in the waveform input to the comparator element is reduced.
The circuit configuration disclosed in Reference 3 also improves the capability to receive runs of identical symbols without error, but the time required for compensating for dc potential variations becomes the sum of the time required for smoothing the detected output and the absolute delay times of the channel selection filter and the detector circuit. In a demodulating circuit that employs high-order filters, rapid dc potential compensation becomes difficult.
The circuit configuration disclosed in Reference 4 likewise improves the capability to receive runs of identical symbols without error, but if rapid dc potential compensation is also performed, the time constants of the integrating circuits that detect the maximum and minimum levels of the detected output must be reduced, so there is still a trade-off between rapid dc potential compensation and the tolerance for long runs of identical symbols.